Friday, November 13, 2026

@convequity Oct 31

Convequity on X

Further thoughts on the $CBRS short-seller report I've already quote-tweeted this short-seller report, but I think it's quite funny. These days, a lot of tech short sellers seem to have a poor understanding of the technology itself. Perhaps they're better at timing market liquidity and identifying moments when sentiment is most vulnerable. Going back to the report's central claim, I think it's arguing that Cerebras hasn't adequately addressed the challenges of using a giant substrate to support an entire wafer, or of maintaining reliable connections across such a large chip. It's similar to the challenges facing $NVDA's Rubin Ultra. The idea is to connect four compute chips, with a combined size roughly eight times the reticle limit. At that scale, thermal expansion becomes a major issue, as does maintaining consistent communication between the chips. For Cerebras, these are certainly significant challenges. That's why it took so many years to turn the original idea into something that actually works. I would say the third-generation Wafer-Scale Engine, WSE-3, was the first generation to become commercially attractive. Earlier generations had lots of problems to work through, much like other chips, for example Google's TPU from v1 to v3. Even WSE-3 hasn't solved everything. One of the biggest remaining issues is parametric yield. The simplest way to explain it is that, when a chip spans an entire wafer, you can't guarantee that every part will operate reliably at the same high frequency. (Frequency is how many cycles per second the chip runs, so a higher frequency means more compute from the same silicon.) You therefore have to lower the operating frequency of the whole system. A normal chipmaker would cut the wafer into many separate dies and set each one's speed on its own. The argument is that those dies could then run at frequencies 50% higher, or perhaps even twice as high. Cerebras keeps the whole wafer as one chip instead, so it gives up some of the compute the same silicon could otherwise deliver. In return, it gets an enormous amount of compute and on-chip memory connected as one wafer-scale chip. Data moves between the cores over wiring on the wafer itself, rather than through slower, more power-hungry links between separate chips. That is what lets Cerebras serve AI models so quickly, especially for inference. That's the trade-off, and parametric yield has been a constraint for Cerebras. The workaround has been to lower the specifications and operating frequency, leaving enough headroom for the system to work reliably. But that also means leaving some of the wafer's potential unused, despite manufacturing it on an expensive, supply-constrained TSMC N5 process, and potentially on more advanced nodes in the future. That's why I find the latest CS-4 rack-level system, using the WSE-3T, interesting. My understanding is that WSE-3T uses the same wafer design as WSE-3 but delivers more than 50% higher performance. They've apparently found new ways to address the parametric-yield issue, allowing them to unlock frequency headroom they previously couldn't use reliably. It looks as though they're actively addressing the problem and making good progress. The earlier implementation may have been suboptimal, but even that version was already demonstrating commercial competitiveness. This is a common problem with short sellers today: they build a thesis around old information while the technology is evolving rapidly. They point to a technical limitation that may still exist, but fail to distinguish between a problem that makes a product unworkable and one that merely reduces its performance. Between roughly 2015 and 2021 or 2022, these issues may genuinely have been showstoppers. By late 2026, I don't think that's necessarily true anymore. They may still hold performance back somewhat, but they don't prevent the product from working. Meanwhile, Cerebras has the advantage of being the only company to have made a wafer-scale chip work. In my view, that benefit outweighs the remaining limitations. The short seller doesn't seem to recognize that distinction. I think this also explains why Oracle, AWS, OpenAI, and other companies have begun testing Cerebras chips this year. The technology seems to be reaching a point where these problems are largely, though not entirely, resolved. Previously, perhaps they were only halfway to a solution, and the product wasn't sufficiently practical. Now that they're much closer, large-scale commercial deployment becomes more attractive to customers. Of course, it remains to be seen how this plays out. They still haven't crossed the deployment threshold I have in mind, and once they do, we may see new problems emerge. For now, though, my sense is that these are well-known issues among people familiar with the technology. The short seller is largely repeating things that those people already understand. The more interesting question is the direction of progress: how quickly are the problems being resolved, and what does that mean for the product's competitiveness? The report doesn't really address that. The rest of the report seems to cover the usual short-seller material, raising fear, uncertainty, and doubt about adoption and other peripheral issues. But the central technical thesis strikes me as quite weak. It reminds me of previous short reports on companies such as $SMCI.