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$TSEM + $SOI: positioned on both sides of the biggest shift in AI datacenter interconnect — and Google's new TPUv8i just supercharged the story. Leg 1 — Smarter optics, much bigger chips. Next-gen optical links ("coherent-lite") encode data far more densely than today's IMDD links. But the sophistication has a physical cost: the photonic chip needs roughly 2–2.5x more silicon area per port, because it packs in multiple modulators, splitters, and detectors where today's simpler links need one of each. Factor in that bigger dies yield worse, and you need ~3–4x the wafer starts per port. More area × more volume × worse yield = several-fold growth in SiPh wafer demand over the cycle. Leg 2 — The switch itself goes photonic. TPUv8i connects its chips through an optical circuit switch (OCS) built from silicon photonics — a genuinely new thing. $GOOGL's old scale-out OCS used MEMS mirrors: zero SiPh content. The new one puts a very large photonic die (300–450mm², heading toward 500–800mm² — near the reticle limit) in every pod. That's a brand-new ~10–20% layer of demand on top of the transceiver story, and it scales faster than linearly as switch radix grows from 64×64 to 128×128. The elegant part: Leg 2 forces Leg 1. The optical switch loses 5–10dB of light — 70–90% of the signal is gone by the time it exits. Today's IMDD transceivers can't read a signal that weak; coherent ones can. So every transceiver plugged into the switch fabric has no choice but to go coherent — and coherent means the 2–2.5x bigger chips from Leg 1. Google's switch decision doesn't just create its own SiPh demand; it automatically triggers the transceiver upgrade too. Tower has manufacturing flows for both legs: high-speed modulator + Ge flows for transceiver PICs, AND mature passive flows for the huge fabric dies. Soitec supplies the photonics-SOI wafers upstream either way — it wins regardless of which foundry takes the socket. One more kicker: Celero, the Alphabet-backed startup tipped for Google's coherent DSP socket, has no fab of its own — its companion photonic chip has to land somewhere, and an open specialty foundry is the obvious somewhere. Risks: coherent modulators migrating to InP/TFLN would leak the PIC leg out of silicon photonics; Marvell verticalizing into its own photonics partially bypasses the open-foundry path.

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Tower Semiconductor Deep Dive

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Capital Wars

CoreWeave’s $35 billion to $39 billion 2026 spending plan relies on debt as unsecured yields reach 15%, making its GPU cloud expansion a…

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Net Interest 12 clicks

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