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NASDAQ

Tower Semiconductor LTD

TSEM

6 stories

$19B Market cap · 2026-10-23

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$TSEM remains one of our highest-conviction holdings, even after we trimmed the position in our 4Q26 rebalance. We wanted to keep Tower at its 6.1% portfolio weight despite a roughly 25% fall in its share price over the past quarter. To make room for new holdings, we trimmed the weight to 4.75% and banked some profits. With SpaceX ($SPCX) also becoming a larger holding, we are limiting further additions to avoid concentrating the portfolio in a few companies. Our confidence in Tower's technology remains strong. We think Tower's competitive advantage comes from combining chips that send and receive data using light with the electronic chips that drive and control them. Next-generation optical connections require these components to exchange more data within a smaller space. Hybrid bonding achieves this by joining the chips through densely packed electrical connections that move large amounts of data in a compact package. In our view, Tower's capabilities here are effectively unmatched among Western suppliers. Tower has also added manufacturing capacity more successfully than we expected. It can fulfill more customer orders itself, leaving less business for $GFS. Customers have less reason to switch to a supplier whose technology they consider weaker when Tower can meet their needs, so the capacity expansion strengthens our Tower thesis and weakens the case for competitors that rely on orders Tower cannot accommodate.
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Judging Tower Semiconductor ($TSEM) by how advanced its chip process is misses what its chips are for. Skeptics often set Tower's older 65 nm process against the more advanced processes at TSMC ($TSM). That yardstick suits logic chips, which are judged on transistor density. It does not suit the analog chips Tower makes for optics. 1. In an optical engine, the analog front-end is the circuitry that drives the laser and reads the returning light. It needs speed, linearity and power efficiency, not maximum transistor density. 2. Tower's strength is its silicon-germanium BiCMOS processes. They have long dominated the merchant market for these laser-driver and receiver chips because they deliver high performance without the most advanced CMOS logic. 3. A less noticed strength is hybrid bonding. Co-packaged optics needs an electronic chip bonded reliably onto a photonic one. Tower already runs mature, high-yield hybrid bonding for stacked image sensors in high-end phones, where a signal-processing chip is bonded onto a light-sensing chip. A close technical parallel, already at volume. The limit: if the electronic chip has to take on more complex signal processing, such as clock recovery or adaptive equalization, TSMC's advanced FinFET processes do offer real advantages in power and integration. Different foundries may end up making different parts of the system. So Tower's position in optics rests on silicon-germanium and photonic process expertise, not on advanced logic.
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$TSEM + $SOI: positioned on both sides of the biggest shift in AI datacenter interconnect — and Google's new TPUv8i just supercharged the story. Leg 1 — Smarter optics, much bigger chips. Next-gen optical links ("coherent-lite") encode data far more densely than today's IMDD links. But the sophistication has a physical cost: the photonic chip needs roughly 2–2.5x more silicon area per port, because it packs in multiple modulators, splitters, and detectors where today's simpler links need one of each. Factor in that bigger dies yield worse, and you need ~3–4x the wafer starts per port. More area × more volume × worse yield = several-fold growth in SiPh wafer demand over the cycle. Leg 2 — The switch itself goes photonic. TPUv8i connects its chips through an optical circuit switch (OCS) built from silicon photonics — a genuinely new thing. $GOOGL's old scale-out OCS used MEMS mirrors: zero SiPh content. The new one puts a very large photonic die (300–450mm², heading toward 500–800mm² — near the reticle limit) in every pod. That's a brand-new ~10–20% layer of demand on top of the transceiver story, and it scales faster than linearly as switch radix grows from 64×64 to 128×128. The elegant part: Leg 2 forces Leg 1. The optical switch loses 5–10dB of light — 70–90% of the signal is gone by the time it exits. Today's IMDD transceivers can't read a signal that weak; coherent ones can. So every transceiver plugged into the switch fabric has no choice but to go coherent — and coherent means the 2–2.5x bigger chips from Leg 1. Google's switch decision doesn't just create its own SiPh demand; it automatically triggers the transceiver upgrade too. Tower has manufacturing flows for both legs: high-speed modulator + Ge flows for transceiver PICs, AND mature passive flows for the huge fabric dies. Soitec supplies the photonics-SOI wafers upstream either way — it wins regardless of which foundry takes the socket. One more kicker: Celero, the Alphabet-backed startup tipped for Google's coherent DSP socket, has no fab of its own — its companion photonic chip has to land somewhere, and an open specialty foundry is the obvious somewhere. Risks: coherent modulators migrating to InP/TFLN would leak the PIC leg out of silicon photonics; Marvell verticalizing into its own photonics partially bypasses the open-foundry path.

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