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Friday, October 16, 2026· 5198 stock ideas· 217 writers·
16,501 views· 7,619 clicks

Is The Market Turning The Page?

CoreWeave’s debt and equity price action is framed as a wake-up call for investors amid a broader market discussion.

CRWV $43B
WHAT ARE WE DOING? “Contrarians At The Gate” 13 clicks

From X

@convequity

Convequity on X

Huawei's finer bonding deserves more weight in the AI-chip race. $AVGO's 3.5D approach combines vertically stacked dies with the side-by-side packaging used to connect processors and HBM. It adds another direction in which designers can shorten the wires moving data around a chip. Besi describes Broadcom's initial face-to-face hybrid bonding at 6µm pitch. Huawei reports 1.5µm for its 2026 Kirin implementation. Pitch is the spacing between connections; face-to-face brings the dies' wiring surfaces together. On an identical square grid, that spacing difference allows 16x as many potential bond sites per unit area. Usable connections still depend on routing and the space reserved for power and repair. It is an architectural opportunity, not a bandwidth multiple. The size qualification matters. Kurnal's Kirin 9050 die shots measure roughly 121mm² per die. Extending fine-pitch bonding to much larger AI dies changes the economics: more expensive silicon is at risk when a stack fails, and heat and power delivery have to work across the whole assembly. Broadcom also said face-to-face compute SoC shipments began in February 2026. A later roadmap cannot be read as its first arrival at face-to-face bonding. Huawei looks ahead on this published pitch comparison. Our view is that this gives it a credible route to narrowing parts of the AI-chip gap through packaging. The stronger claim needs production evidence at large accelerator scale. The phone result alone does not establish when that arrives. Builds on Convequity's Huawei After Sanctions, Parts 1–2, 10 & 18 Sep 2026, with updated source checks.

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