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Sunday, November 1, 2026

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@convequity

Convequity on X

Kirin 9050 Pro is the first Tau Scaling chip. The bigger story is Ascend. Huawei just put LogicFolding in the Mate XT 2. First commercial SoC on the Tau (τ) law He Tingbo laid out in May / updated in July. Not a surprise if you read that paper. Still a real jump: DUV + SAQP + logic stacking took density from 155 → 238 MTr/mm² on the same SMIC N+3 node. +55% in one gen. Power went down, not up. That’s N3-class equivalent density. Headline number matches Intel 18A HD (238) and sits next to Samsung SF2 (~231). TSMC N2 HD is still ahead (~313). Caveat: 238 is Huawei’s LogicFolding equivalent, not a planar N3 shrink. Same device node as 9030 Pro. Some analysts put the industry-formula read closer to ~175. Mobile scoreboard vs last-gen trifold / 9030 Pro: • Device +42% • CPU ST +24% / MT +52% • P-core 3.1 GHz (was 2.75) • CPU / GPU / NPU iso-perf power −41% / −58% / −66% • GPU render +142% • On-device 30B-total-param MoE Multi-core still trails $QCOM’s latest. The gap is no longer multi-generation. Next Tau Kirin can catch, maybe pass, a leading-edge mobile SoC. The packaging tell is sharper than the phone benches. 1.4–1.5μm hybrid-bond pitch. ~50M vertical interconnects. Western HVM hybrid bonding is still ~6μm (TSMC SoIC) to ~9μm (Intel Foveros Direct). If 1.4μm holds, that is SOTA vs Western leading-edge bonding — not the Geekbench print. Phone catch-up is the demo. AI silicon is the payoff. Apply the same fold to Ascend and the process-density gap vs $NVDA peers compresses from the lithography side over the next few quarters. Remaining bottlenecks: domestic DUV tool volume, HBM, packaging, software. I wouldn’t assume they outproduce ASML on DUV. I also wouldn’t fade the direction. Mature DUV + stacking + almost-unlimited power is enough to put China in the token-factory fight vs the US. Tables below. 🧵

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