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Monday, October 19, 2026

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3D chips could create more room for specialist EDA startups. We are not convinced that more difficult chip design automatically translates into a large revenue windfall for $SNPS, $CDNS and Siemens. Fine-pitch stacking changes decisions that used to be made within one die. Put a circuit upstairs and its wires may get shorter, but its heat affects the circuit below. Placement, signal timing and power delivery have to be optimized together across the stack. That creates a reason for $AVGO and $NVDA to build custom tools around their architectures. Broadcom already describes a proprietary design flow built on industry-standard tools. Nvidia publishes its own research on assigning connections across tiers in 3D chips. Our inference is that the chip designers will keep some of the most differentiating optimization work in-house. A startup that solves a costly gap in cross-die planning or optimization could also win business without replacing an entire EDA suite. The incumbents still supply implementation, verification and manufacturing sign-off tools, and they are developing 3D capabilities themselves. Internal tooling is evidence that customers need more than the standard flow; it does not establish that incumbent spending falls. We see a more interesting startup opportunity where a tool can shorten repeated design iterations or improve the resulting chip enough to earn a separate budget. That is the part of the 3D transition we would investigate before assuming the largest EDA vendors capture most of the upside.

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