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Friday, October 16, 2026· 5206 stock ideas· 217 writers·
16,553 views· 7,627 clicks

Is The Market Turning The Page?

CoreWeave’s debt and equity price action is framed as a wake-up call for investors amid a broader market discussion.

CRWV $43B
WHAT ARE WE DOING? “Contrarians At The Gate” 15 clicks

From X

@convequity

Convequity on X

$NVDA: custom ASICs eat into the GPU share Our scenarios include custom ASICs rising from roughly 20% of the overall AI compute mix toward 40–50%. ABBX records 21.2GW of planned capacity for OpenAI and 13.8GW for Anthropic. Within Anthropic’s plan, ABBX allocates 5GW to AWS Trainium and 5GW to Google/Broadcom TPUs, putting these custom-chip platforms at roughly 72% of its planned capacity. That is a substantial shift in hardware demand if the deployments proceed, although the plans span different timelines. With purchasing concentrated among a few large customers, their decisions to expand on custom silicon could reduce NVIDIA’s share of spending even as the overall AI infrastructure market continues to grow.
@convequity

Convequity on X

$SITM supplies timing devices used in optical modules in NVIDIA-based AI data centers. In an AI data center, a clock exists to keep parts synchronized. Training and inference run across thousands of chips in parallel, and each step depends on data arriving at the right moment. When timing slips, GPUs wait, networks stall, and expensive compute goes unused. The move from 800G to 1.6T optical modules shows how this becomes demand for timing parts. Bandwidth does not simply double. The link is split into more lanes running at higher baud rates. Each lane has a tighter jitter budget, and it often adds clock domains for the DSPs, SerDes groups and laser drivers. So each module carries more timing components, and each component has to meet a higher performance requirement. That pushes average selling prices up alongside unit volumes. The same pattern appears in the switches inside that cluster. A high-radix switch multiplies SerDes lanes as bandwidth scales. When the switch increases radix and speed at the same time, it drives more clock domains across the fabric, the ports, and the control logic. Timing content in the switch therefore multiplies rather than rising in step with the size of the cluster. This is why we see continued hypergrowth for SiTime. In NVIDIA-based data centers, SiTime's parts are discrete devices, separate from the GPU and switch ASICs, allowing timing performance to improve independently as system requirements change, and demand for them rises in several places in the rack at once.

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